/* zet_ff */

module zet_ff
(
	input clk,
	input rst,
	input rst_value,

	input d,
	output q
	//output q_bar
);

	reg __q;

	assign q = __q;

	// Behaviour
	always @(posedge clk)
	begin
		if(rst)
		begin
			__q <= rst_value;
		end

		else
			begin
				__q <= d;
				//q_bar <= !d;
			end
	end

endmodule

